Automatic interface synthesis based on the classification of interface protocols of IPs

• Published in: 2008 Asia and South Pacific Design Automation Conference pp. 589 - 594
• Main Authors: Chang Ryul Yun, DongSoo Kang, YoungHwan Bae, HanJin Cho, Kyoung Son Jhang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2008
• Subjects: Buffer storage; Circuit synthesis; Clocks; Computer buffers; Delay; Design methodology; Protocols; Registers; Signal synthesis; System-on-a-chip
• ISBN: 1424419212; 9781424419210
• ISSN: 2153-6961; 2153-697X
• DOI: 10.1109/ASPDAC.2008.4484020

In a system on a chip (SoC) design, we use an IP-based design methodology to reduce design time. An interface circuit design is one of the most essential factors in IP-based design. However, it is not easy to generate interface circuits because IPs have various characteristics. For example, one IP may send only one outstanding address in a burst but another IP may need one address for each transfer in a burst. IPs also use different clock frequencies or different data widths. It is necessary to analyze the interface protocols of each IP to consider and resolve these differences during synthesis. In this paper, we categorize the various interface protocols and use the synthesis algorithm to select the appropriate structure based on the categorizations, clock frequencies, and data width differences of the IPs. Through the experiments, we show that we could automatically generate interface circuits for IPs with different clocks, different data widths, and no address concepts. Experiments also show the pros and cons of two structures based on the comparisons of the synthesis results of several IP pairs which could be employed between two alternative structures, namely, product FSM-based structure and FSMD-like structure.