Benchmarking TFET from a circuit level perspective: Applications and guideline
Low power applications have led to a boom in researches on new circuits based on steep-slope transistors, of which the objective is to overcome MOSFET's drawback of inevitable increasing leakage power while maintaining acceptable performance in low voltage operation. Among those emerging transi...
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Published in | 2017 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 4 |
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Main Authors | , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.05.2017
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Subjects | |
Online Access | Get full text |
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Summary: | Low power applications have led to a boom in researches on new circuits based on steep-slope transistors, of which the objective is to overcome MOSFET's drawback of inevitable increasing leakage power while maintaining acceptable performance in low voltage operation. Among those emerging transistors, Tunnel FET (TFET) becomes a most promising one due to its low off current and compatibility with CMOS process. In order to guide the application and the improvement of TFET, in this paper from a circuit-level perspective, utilizing a newly defined benchmarking method, we figured out the frequency-VDD range in which Si TFET circuits show low power advantage over their MOSFET counterparts based on HSPICE simulations using calibrated compact model. A systematic and quantitative analysis was then conducted to further enlarge the application scope of TFET circuits, with a Figure of Merit (FOM) and a guideline for future TFET proposed. |
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ISSN: | 2379-447X |
DOI: | 10.1109/ISCAS.2017.8051028 |