Benchmarking TFET from a circuit level perspective: Applications and guideline

Low power applications have led to a boom in researches on new circuits based on steep-slope transistors, of which the objective is to overcome MOSFET's drawback of inevitable increasing leakage power while maintaining acceptable performance in low voltage operation. Among those emerging transi...

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Bibliographic Details
Published in2017 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 4
Main Authors Lingyi Guo, Le Ye, Cheng Chen, Qianqian Huang, Libo Yang, Zhu Lv, Xia An, Ru Huang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2017
Subjects
Delays
Guidelines
Ions
Low power
MOSFET
Power Delay Product
Propagation delay
Switching circuits
TFET
TFET circuit
TFET FOM
TFET guideline
TFETs
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Summary:Low power applications have led to a boom in researches on new circuits based on steep-slope transistors, of which the objective is to overcome MOSFET's drawback of inevitable increasing leakage power while maintaining acceptable performance in low voltage operation. Among those emerging transistors, Tunnel FET (TFET) becomes a most promising one due to its low off current and compatibility with CMOS process. In order to guide the application and the improvement of TFET, in this paper from a circuit-level perspective, utilizing a newly defined benchmarking method, we figured out the frequency-VDD range in which Si TFET circuits show low power advantage over their MOSFET counterparts based on HSPICE simulations using calibrated compact model. A systematic and quantitative analysis was then conducted to further enlarge the application scope of TFET circuits, with a Figure of Merit (FOM) and a guideline for future TFET proposed.
ISSN:2379-447X
DOI:10.1109/ISCAS.2017.8051028