Thermal qualification of 3D stacked die structures

After an introductory discussion of the thermal issues in stacked die packages in general, two major subjects are discussed in the paper: the qualification of die attach in stacked die structures and the questions of compact thermal modeling. An overview is given about the currently used techniques...

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Bibliographic Details
Published in2006 International Biennial Baltic Electronics Conference pp. 1 - 8
Main Author Rencz, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2006
Subjects
Conducting materials
Conductive films
Electronic packaging thermal management
Electronics packaging
Integrated circuit packaging
Microassembly
Qualifications
Silicon
Thermal management
Thermal resistance
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Summary:After an introductory discussion of the thermal issues in stacked die packages in general, two major subjects are discussed in the paper: the qualification of die attach in stacked die structures and the questions of compact thermal modeling. An overview is given about the currently used techniques for the qualification of the die attach for failure analysis in stacked structures. The third part of the paper presents the state-of-the-art and the major issues of compact thermal modeling of stacked die packages. A methodology is suggested for the transient compact modeling of stacked die structures
ISBN:1424404142
9781424404148
ISSN:1736-3705
DOI:10.1109/BEC.2006.311052