A four-megacycle, 24-bit checked binary adder

• Published in: 2nd Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1961) pp. 250 - 265
• Main Author: Homan, M. E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.1961
• Subjects: Clocks; Logic; Solid state circuits
• DOI: 10.1109/FOCS.1961.3

The logical design of a 24-bit binary adder applicable to Stretchtype computers is described. Solid-state, nanosecond logical elements employing diffused-junction transistors are used in current-mode and emitter-follower configurations. Parallel carry generation and preformed sum-selecting functions for four-bit subgroups are utilized for maximum speed. The higher component count is more than offset by the increased performance over adders of more conventional design. Storage, gating, and half-sum generation elements are parity checked in six-bit groups. Carry and sum generation are checked by redundant serial carry logic operating in an "after-the-fact" mode. Checking logic is performed in parallel with adding and storage operations and therefore does not penalize performance. Additions are completed in a relatively fixed time interval because of the parallel carry system and the nature of the logical elements employed. Asynchronous control provides no special advantage where such characteristics hold, and a clock source of symmetrical samples is provided for control. A complete add operation, including storage in transistor registers, can be performed in 250 nanoseconds.