TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects

Some cell-internal defects can be modeled as small delay faults. This paper presents a timing-aware gate exhaustive transition fault (TARGET) ATPG for cell-internal defects. Our ATPG tries to launch gate output transitions from as many different gate input transitions as possible. We defined TARGET...

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Bibliographic Details
Published inVLSI Design, Automation and Test(VLSI-DAT) pp. 1 - 4
Main Authors Ang-Feng Lin, Kuan-Yu Liao, Kuan-Ying Chiang, Li, James Chien-Mo
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2015
Subjects
ATPG
Automatic test pattern generation
cell-internal defect
Circuit faults
Computer architecture
Delays
FinFETs
Graphics processing units
Logic gates
small delay faults
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Summary:Some cell-internal defects can be modeled as small delay faults. This paper presents a timing-aware gate exhaustive transition fault (TARGET) ATPG for cell-internal defects. Our ATPG tries to launch gate output transitions from as many different gate input transitions as possible. We defined TARGET coverage and TARGET SDQL to evaluate the quality of our test sets. TARGET does not require exhaustive SPICE simulation to characterize each library cell. Compared with traditional N-detect and timing-aware test patterns, the proposed TARGET test patterns have better TARGET coverage given the same test length.
DOI:10.1109/VLSI-DAT.2015.7114503