Design and analysis of low power open core protocol compliant interface using VHDL

• Published in: 2011 International Conference on Emerging Trends in Electrical and Computer Technology pp. 621 - 625
• Main Authors: Bhakthavatchalu, R, Deepthy, G R, Vidhya, S, Nisha, V
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2011
• Subjects: Bridges; Bus Bridge; I2C Controller; Interface; IP networks; Master; OCP compliant; Process control; Processor; Protocols; Registers; Slave; System-on-a-chip; Timing

The necessity of Intellectual Properties (IP) reuse to shorten the design time and the complexity makes the large scale System On Chip (SoC) more challenging. An efficient bus protocol for the core communication between IP block is OCP. Open Core Protocol (OCP) defines the only non-proprietary, open...