Two-transistor Voltage-Measurement-Based Test Structure for Fast Extraction of MOS Mismatch Design Parameters

• Published in: 2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) pp. 114 - 119
• Main Authors: Brito, Juan Pablo Martinez, Bampi, Sergio
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2019
• Subjects: Conferences; Current measurement; Mathematical model; Microelectronics; MOSFET; Semiconductor device measurement; Transistor Mismatch Measurements. Stacked-Pair MOSFET. Linear regression analysis
• ISBN: 9781728114644; 1728114640
• ISSN: 1071-9032; 2158-1029
• DOI: 10.1109/ICMTS.2019.8730918

This paper proposes a new test structure and a measurement method for measuring MOS transistors mismatches. The structure is based on the combination of two stacked MOS transistors and the measurement methodology relies on two single DC voltage measurements. The method allows to extract separately \sigma(\triangle V_{TH}) and \sigma(\Delta\beta/\beta) and enables fast extraction of design MOS mismatch parameters such as A_{V_{TH}} and A_{\beta} with less than 2% error. The simple data post-processing algorithm results in an increase of \pmb{30\mathrm{x}} in the measurement speed with data correlation coefficient not less than 0.94 (R^{2}\geq \pmb{0.94}) . Rapid address decoding and bias configuration have been used in order to select each device in a two-dimensional (2D) DUT matrix of FETs. The experimental data presented herein for analysis is taken from measurements in a prototype fabricated in 65nm CMOS bulk process.