Fabrication of package level silicon micro-cooler for electronics cooling

• Published in: 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) pp. 1 - 7
• Main Authors: Lau, B. L., Yong Han, Gong Yue, Zhang Lu, Zhang Xiaowu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2015
• Subjects: Bonding; Cooling; Etching; Metals; Microchannels; Silicon
• DOI: 10.1109/EPTC.2015.7412309

In this paper, the fabrication of package level silicon micro-cooler for electronics cooling is presented. These include the design, micro fabrication process of silicon flow channels chip and chip level integration of a hybrid silicon micro-cooler, which integrates jet impingement, multiple input-output crossflow channels and microchannel cooling technologies. The components of silicon micro-cooler are fabricated using silicon semiconductor process. The jet nozzle arrays, micro fins and channels are fabricated using through silicon vias (TSV) and deep reactive etching (DRIE) process technologies. The device thermal chip and three silicon-coolers chip are bonded together using thermal compression bonding (TCB). Several approaches were carried out to study the strength of eutectic bonding interface such as AuIn and AuSn staked layers which processed by IME in-house equipments. The TCB process parameters were optimized and the sequences of chip bonding process flows conditions were identified to reach the best bonding strength. The PCB and liquid manifold package onto the micro-cooler are introduced later to achieve leakage free condition. In this paper, the major fabrication steps and critical process parameters will be discussed in details along with the mechanical hydraulic test and thermal analysis of both heat sinks for comparison. The reliability and moisture test also show positive results after went through thermal cycles.