A heterogeneous time-triggered architecture on a hybrid system-on-a-chip platform

• Published in: 2016 IEEE 25th International Symposium on Industrial Electronics (ISIE) pp. 244 - 253
• Main Authors: Isakovic, Haris, Grosu, Radu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2016
• Subjects: Computer architecture; Computers; Field programmable gate arrays; Hardware; Performance evaluation; Safety; System-on-chip
• ISSN: 2163-5145
• DOI: 10.1109/ISIE.2016.7744897

There is a huge discrepancy between off-the-shelf (COTS) hardware architectures and requirements for embedded industrial applications. Industrial systems are getting more complex by the day, and an interaction of highly diverse components within these systems is unavoidable. An implementation of such systems on COTS hardware is challenging. Platforms based on single-core CPUs is becoming limited, and use of multicore architectures yields safety risks, and overall inefficiency. Tailored architectures provide adequate service but they lack flexibility and therefore their economic justification is limited. Emerging technologies i.e., hybrid system-on-chip combined with novel architectural concepts are filling blind spots between COTS architectures and embedded industrial applications. The paper presents the implementation of an MPSoC architecture on a hybrid system-on-a-chip platform. This architecture provides unique capabilities for embedded applications, in particular, the possibility to host mixed-criticiality and cross-domain applications.