Finite Precision Analysis of the 3GPP Standard Turbo Decoder for Fixed-Point Implementation in FPGA Devices

FPOAs are reconfigurable devices similar to FPGAs but offer a much higher level of abstraction than the gate level. The main advantage of FPOAs is their deterministic on chip network, which guarantees that an application executes at the design frequency. Mathstarpsilas current toolflow requires cons...

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Bibliographic Details
Published in2008 International Conference on Reconfigurable Computing and FPGAs pp. 43 - 48
Main Authors Morales-Cortes, A., Parra-Michel, R., Gonzalez-Perez, L.F., Cervantes, T.G.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2008
Subjects
Algorithm design and analysis
Code standards
Communication standards
Convolutional codes
Decoding
Digital signal processing
Field programmable gate arrays
Fixed-point arithmetic
Hardware
Turbo codes
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Summary:FPOAs are reconfigurable devices similar to FPGAs but offer a much higher level of abstraction than the gate level. The main advantage of FPOAs is their deterministic on chip network, which guarantees that an application executes at the design frequency. Mathstarpsilas current toolflow requires constant manual guidance to place and route a design. In this paper we propose a finite domain Constraint Satisfaction (CS) based approach, which considers the communication delay between hardware resources to ensure that they meet the designpsilas timing requirement. We tested our Placement tool using a parameterized design test generator, and a 48-tap FIR filter. The tool reported a feasible solution for problems with known solutions, typically within a few seconds.
ISBN:9781424437481
1424437482
ISSN:2325-6532
2640-0472
DOI:10.1109/ReConFig.2008.82