Impact of Epi-Si growth temperature on Ge-pFET performance

In this study, we report a direct comparison between two epitaxial silicon processes: 500degC using SiH 4 and 350degC using Si 3 H 8 . Following four different metrics, we demonstrate that the reduction of silicon growth temperature results into the introduction of negatively charged defects possibl...

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Bibliographic Details
Published in2009 Proceedings of the European Solid State Device Research Conference pp. 411 - 414
Main Authors Mitard, J., Martens, K., DeJaeger, B., Franco, J., Shea, C., Plourde, C., Leys, F.E., Loo, R., Hellings, G., Eneman, G., Wei-E Wang, Lin, J.C., Kaczer, B., DeMeyer, K., Hoffmann, T., DeGendt, S., Caymax, M., Meuris, M., Heyns, M.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2009
Subjects
Dielectrics and electrical insulation
High K dielectric materials
High-K gate dielectrics
III-V semiconductor materials
Inorganic materials
Interface states
Semiconductor films
Silicon
Temperature dependence
Temperature measurement
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Summary:In this study, we report a direct comparison between two epitaxial silicon processes: 500degC using SiH 4 and 350degC using Si 3 H 8 . Following four different metrics, we demonstrate that the reduction of silicon growth temperature results into the introduction of negatively charged defects possibly located at the Si/SiO 2 interface. However, the Epi Si growth at 350degC with Si 3 H 8 remains beneficial compared to a growth performed at 500degC-SiH 4 especially when thin EOT Ge pFETs are targeted.
ISBN:9781424443512
1424443512
ISSN:1930-8876
DOI:10.1109/ESSDERC.2009.5331351