A 40 nm 535 Mbps multiple code-rate turbo decoder chip using reciprocal dual trellis

• Published in: 2012 IEEE Asian Solid State Circuits Conference (A-SSCC) pp. 197 - 200
• Main Authors: Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2012
• DOI: 10.1109/IPEC.2012.6522659

This paper presents a turbo decoder chip which can decode code rate k/(k + 1) constituent convolutional codes for k =1, 2, 4, 8, and 16. After replacing the constituent code by its code rate 1/(k + 1) reciprocal dual code, we can derive a smaller codeword space and design a simpler decoding trellis structure for high code-rate SISO decoder. In addition, two parallel SISO decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm 2 core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.