Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique

This paper presents a die-level post-CMOS processing protocol for multi-layer homogeneous 3D integration with adhesive bonding technique using parylene-C as an intermediate bonding layer and sidewall passivation material. This protocol was used to fabricate 4-layer CMOS memory chip stacks, which wer...

Full description

Saved in:
Bibliographic Details
Published in2016 IEEE International 3D Systems Integration Conference (3DIC) pp. 1 - 5
Main Authors Kucuk Eroglu, S. E., Choo, W. Y., Leblebici, Y.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2016
Subjects
3D integration
adhesive bonding
Bonding
Copper
copper TSV
die-level integration
Etching
parylene-C
post-CMOS processing
Semiconductor device measurement
Three-dimensional displays
Through-silicon vias
Online AccessGet full text

Cover

More Information
Summary:This paper presents a die-level post-CMOS processing protocol for multi-layer homogeneous 3D integration with adhesive bonding technique using parylene-C as an intermediate bonding layer and sidewall passivation material. This protocol was used to fabricate 4-layer CMOS memory chip stacks, which were then packaged and tested using time domain reflectometry (TDR) measurement technique. The results have showed that the characteristic inductance values were improved for 3D integrated memory chips due to the elimination of bonding wires.
DOI:10.1109/3DIC.2016.7970016