ESD protection networks for 3D integrated circuits

The inter-die signal interfaces in a 3D-IC are vulnerable to over-voltage stress induced by Charged Device Model ESD. The magnitude of the stress is highly sensitive to the design of the ground distribution network on both the die and package level. It is also affected by the type of package being u...

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Bibliographic Details
Published in2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International pp. 1 - 7
Main Authors Rosenbaum, E., Shukla, V., Min-Sun Keel
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2012
Subjects
Charged Device Model
Clamps
Discharges (electric)
Electrostatic discharge
Electrostatic discharges
Integrated circuit modeling
Receivers
Stress
Through-silicon vias
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Summary:The inter-die signal interfaces in a 3D-IC are vulnerable to over-voltage stress induced by Charged Device Model ESD. The magnitude of the stress is highly sensitive to the design of the ground distribution network on both the die and package level. It is also affected by the type of package being used. Small voltage clamping devices may be placed at inter-die receivers to mitigate the risk of gate dielectric breakdown. New ESD rule checking tools are needed for 3D-IC design automation.
ISBN:9781467321891
1467321893
DOI:10.1109/3DIC.2012.6262965