Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling

This paper proposes a novel strategy for enabling dynamic task mapping on heterogeneous NoC-based MPSoC architectures. The solution considers three different platforms with different area constraints and applications with distinct efficient characteristics. We propose a solution that uses a unified...

Full description

Saved in:
Bibliographic Details
Published in6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC) pp. 1 - 8
Main Authors Ost, L., Almeida, G. M., Mandelli, M., Wachter, E., Varyani, S., Sassatelli, G., Indrusiak, L. S., Robert, M., Moraes, F.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2011
Subjects
Context
design space exploration of heterogeneous MPSoCs
dynamic mapping
Energy consumption
Field programmable gate arrays
Hardware
Heuristic algorithms
modeling
NoC-based MPSoCs
Program processors
Unified modeling language
Online AccessGet full text

Cover

More Information
Summary:This paper proposes a novel strategy for enabling dynamic task mapping on heterogeneous NoC-based MPSoC architectures. The solution considers three different platforms with different area constraints and applications with distinct efficient characteristics. We propose a solution that uses a unified model-based framework, which is calibrated according to area information obtained from FPGA synthesis. Besides, we present the performance of various applications running on different processors on FPGAs aiming to obtain application efficiency characteristics for calibrating the proposed high-level model. The paper also presents three different scenarios and discusses the reduction in terms of energy consumption as well as the end-to-end communication cost for different applications such as MPEG and ADPCM, among others multimedia benchmarks.
ISBN:1457706407
9781457706400
DOI:10.1109/ReCoSoC.2011.5981517