A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

A 7.7mW/1.0ns/1.35V digital delay locked loop has been proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power operation and low jitter, which is primarily caused by the length of the delay line. The merged dual coarse delay line (MDCDL) is employed fo...

Full description

Saved in:
Bibliographic Details
Published in2010 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 3861 - 3864
Main Authors Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jong Ho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2010
Subjects
Delay lines
Detectors
Energy consumption
Frequency
Jitter
Logic gates
Power engineering and energy
Random access memory
SDRAM
Shift registers
Online AccessGet full text

Cover

More Information
Summary:A 7.7mW/1.0ns/1.35V digital delay locked loop has been proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power operation and low jitter, which is primarily caused by the length of the delay line. The merged dual coarse delay line (MDCDL) is employed for low power and high frequency operation. This DLL utilizes an OR-AND DCC for wide duty cycle correction capability. The proposed DLL for DDR3 SDRAM is fabricated by a 54nm DRAM process technology. Experimental results show that ±10% duty error of external clock can be corrected in less than 400 cycles locking time with 1.0GHz operation frequency at 1.35V.
ISBN:1424453089
9781424453085
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2010.5537703