Scaling of BTI reliability in presence of time-zero variability

In this paper, we first outline the impact of Bias Temperature Instability (BTI) on the transistor threshold voltage as a function of time and the gate oxide field. Subsequently, the correlation between time-zero and time-dependent variability is described. A combined distribution encompassing both...

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Bibliographic Details
Published in2014 IEEE International Reliability Physics Symposium pp. CA.5.1 - CA.5.7
Main Authors Kukner, Halil, Weckx, Pieter, Franco, Jacopo, Toledano-Luque, Maria, Moonju Cho, Kaczer, Ben, Raghavan, Praveen, Doyoung Jang, Miyaguchi, Kenichi, Bardon, Marie Garcia, Catthoor, Francky, Van der Perre, Liesbet, Lauwereins, Rudy, Groeseneken, Guido
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2014
Subjects
Acceleration
Aging
Bias Temperature Instability
channel material
Degradation
FET
FinFET
FinFETs
Logic gates
reliability
scaling
Silicon
Stress
time-zero variability
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Summary:In this paper, we first outline the impact of Bias Temperature Instability (BTI) on the transistor threshold voltage as a function of time and the gate oxide field. Subsequently, the correlation between time-zero and time-dependent variability is described. A combined distribution encompassing both contributions with their relative weights is derived. Finally, circuit-level insights on the BTI impact are given based on case study simulations of Ring Oscillators (ROs) at commercial-grade 28nm planar and research-grade 14, 10, 7nm FinFET technology nodes for several FET channel materials (e.g. Si, SiGe, Ge, InGaAs).
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2014.6861122