One-Step Compilation of Image Processing Applications to FPGAs

This paper describes a system for one-step compilation of image processing (IP) codes, written in the machine-independent, algorithmic, high-level single assignment language SA-C, to FPGA-based hardware. The SA - C compiler performs a variety of optimizations, some conventional and some specialized,...

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Published inThe 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01) pp. 209 - 218
Main Authors Bohm, A.P.W., Draper, B., Najjar, W., Hammes, J., Rinker, R., Chawathe, M., Ross, C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
Chromium
Computational modeling
Computed tomography
Field programmable gate arrays
Image processing
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Summary:This paper describes a system for one-step compilation of image processing (IP) codes, written in the machine-independent, algorithmic, high-level single assignment language SA-C, to FPGA-based hardware. The SA - C compiler performs a variety of optimizations, some conventional and some specialized, before generating dataflow graphs and host code. The dataflow graphs are then compiled, via VHDL, to FPGA configuration codes. This paper introduces SA - C and describes the optimization and code generation stages in the compiler. The performance of a target acquisition prescreener (ARAGTAP), the Intel Image Processing Library, and an iterative tri-diagonal solver running on a reconfigurable system are compared to their performance on a Ppentium PC with MMX.
ISBN:9780769526676
0769526675