A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL

A novel frequency search algorithm is proposed in this paper to achieve fast locking in all digital PLL (ADPLL) with no phase tracking being required. According to phase and frequency error, the normalized tuning word (NTW) is calculated so that the output frequency reaches the desired frequency imm...

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Bibliographic Details
Published in2013 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 2464 - 2467
Main Authors Bohan Wu, Weixin Gai, Te Han
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2013
Subjects
Bandwidth
Estimation error
Frequency estimation
Measurement uncertainty
Phase frequency detector
Phase locked loops
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Summary:A novel frequency search algorithm is proposed in this paper to achieve fast locking in all digital PLL (ADPLL) with no phase tracking being required. According to phase and frequency error, the normalized tuning word (NTW) is calculated so that the output frequency reaches the desired frequency immediately. As the non-idealities, such as DCO gain estimation error and TDC finite resolution, greatly affect the accuracy of the calculation, the output frequency is continuously measured and frequency error is averaged to minimize those impacts. With 0.13um CMOS process, the proposed ADPLL operates at 2.7 GHz and achieves 0.35 us locking time while consuming 7.47mW.
ISBN:9781467357609
146735760X
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2013.6572378