Low-power high-speed multiplier for error-tolerant application

In this paper, a new design concept that engaged accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, the bottleneck of conventional digital IC design techniques can be breakthrough to improve on the performances of power consumption and speed. The aim is to ful...

Full description

Saved in:
Bibliographic Details
Published in2010 IEEE International Conference of Electron Devices and Solid-State Circuits pp. 1 - 4
Main Authors Khaing Yin Kyaw, Wang Ling Goh, Kiat Seng Yeo
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2010
Subjects
Accuracy
CMOS technology
Educational institutions
error-tolerant
high speed integrated circuits
Logic gates
low power
Multiplier
truncated
Online AccessGet full text

Cover

More Information
Summary:In this paper, a new design concept that engaged accuracy as a design parameter is proposed. By introducing accuracy as a design parameter, the bottleneck of conventional digital IC design techniques can be breakthrough to improve on the performances of power consumption and speed. The aim is to fulfill the need for high performance basic sequential elements with low-power dissipation which is steadily growing.
ISBN:9781424499977
1424499976
DOI:10.1109/EDSSC.2010.5713751