Advanced multi-high-operation-voltage I/O device design for 32nm gate-first HiK MG technology

This paper presents the advanced I/O device design for 32 nm Hi-K Metal Gate technology with multi-high operation voltages. Process optimization work is done on the I/O composite gate dielectric stack to improve TDDB Vmax. By using advanced junction engineering, 3.3 V device Isubmax is reduce by 30-...

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Bibliographic Details
Published in2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) pp. 1 - 4
Main Authors Xusheng Wu, Hu, Y, Kusunoki, N, Yang, Z J, Yang, G, Teh, Y, Kirshnan, R, Krishnan, S, Shepard, J, Han, S, Lee, Y, Arnaud, F, Sherony, M, Sudijono, J, Steegen, A
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2010
Subjects
HCI
HiK Metal Gate
Human computer interaction
I/O
Junction Engineering
Junctions
Logic gates
Optimization
Performance evaluation
Reliability
TDDB
Transistors
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Summary:This paper presents the advanced I/O device design for 32 nm Hi-K Metal Gate technology with multi-high operation voltages. Process optimization work is done on the I/O composite gate dielectric stack to improve TDDB Vmax. By using advanced junction engineering, 3.3 V device Isubmax is reduce by 30-40% without Ion degradation based on TCAD simulation guideline. At the same time, 2.5 V device drive current and DIBL performance are maintained without degradations. Reliability stress testing result further confirms the inline electrical result with same trend. 3.3V I/O TDDB, HCI, and BTI results are reported.
ISBN:9781424499977
1424499976
DOI:10.1109/EDSSC.2010.5713769