Effective Signal Restoration in Post-Silicon Validation

Trace buffer based run-time techniques have been proposed and widely applied to post-silicon validation for bug detection and localization after post-manufacturing testing. However, hardware overhead limits the size of the trace buffer, i.e. the number of signals traced during run-time. In order to...

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Bibliographic Details
Published in2017 IEEE International Conference on Computer Design (ICCD) pp. 169 - 176
Main Authors Xiaobang Liu, Vemuri, Ranga
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2017
Subjects
Backward justification
Clocks
Forward propagation
Integrated circuit modeling
Logic circuits
Logic gates
Observability
Reconvergent fanout
Restoration ratio
Satisfiability
Signal restoration
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Summary:Trace buffer based run-time techniques have been proposed and widely applied to post-silicon validation for bug detection and localization after post-manufacturing testing. However, hardware overhead limits the size of the trace buffer, i.e. the number of signals traced during run-time. In order to alleviate this limitation, maximal state restoration based on the data stored in trace buffer is desirable with minimal compromise in efficiency. Forward propagation and backward justification (FB) methods were commonly employed and satisfiability-based (SAT) techniques were recently introduced for signal restoration. In this paper, we propose efficient heuristics based on the structure of the circuit and a signal ordering technique for signal restoration using hybrid FB and SAT methods. Experimental results show that our reconvergent fanout based algorithm can achieve up to 72% improvement and our signal ordering heuristic can attain 77.9% improvement compared to the state-of-the-art methods while maintaining optimal restoration ratio.
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2017.34