FPGA Design and Implementation of Missile-Borne SAR Azimuth Filtering

In Missile-borne SAR real-time image signal processing, pre-filtering is usually used to ensure image quality while reducing data redundancy. In order to solve high real-time problem in Missile SAR, this paper proposed an improved FPGA implementation for azimuth filtering. Parallel sub-filter is use...

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Bibliographic Details
Published in2018 China International SAR Symposium (CISS) pp. 1 - 3
Main Authors Ma, Tingting, Hu, Xianhong, Wang, Jing
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2018
Subjects
Azimuth
Band-pass filters
Field programmable gate arrays
Finite impulse response filters
Low pass filters
Real-time systems
SAR algorithm pre-filter
sub-filter
Time division multiplexing
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Summary:In Missile-borne SAR real-time image signal processing, pre-filtering is usually used to ensure image quality while reducing data redundancy. In order to solve high real-time problem in Missile SAR, this paper proposed an improved FPGA implementation for azimuth filtering. Parallel sub-filter is used to reduce the processing time; time division multiplexing is played on the sub-filter used to optimize the organization; Block RAM site operator is used to reduce storage space. Test results show that the high resource utilization and high calculation speed of this method can achieve real-time Missile SAR implementation.
DOI:10.1109/SARS.2018.8551962