A high-throughput and size-efficient NoC buffer design method

This paper presents a high-throughput and size efficient buffer design method for an application specific NoC. The method firstly configures on chip buffer according with the mapping position of IP and the routing path of communication pairs, then computes the minimum value of buffer's size und...

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Bibliographic Details
Published in2012 International Conference on Systems and Informatics (ICSAI2012) pp. 4 - 7
Main Authors Wenbiao Zhou, Zhenyu Liu, Yanjun Zhang, Siye Wang, Dake Liu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2012
Subjects
Algorithm design and analysis
Buffer
Calculus
Design methodology
IP networks
Multiplexing
Network Calculus
NoC
Routing
Throughput
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Summary:This paper presents a high-throughput and size efficient buffer design method for an application specific NoC. The method firstly configures on chip buffer according with the mapping position of IP and the routing path of communication pairs, then computes the minimum value of buffer's size under NoC performance guarantee. Under the same buffer size, the experiments show that the method results in the 40% improvement of the throughput when compared the common input buffer design method.
ISBN:9781467301985
1467301981
DOI:10.1109/ICSAI.2012.6223160