Electromigration-Induced Bit-Error-Rate Degradation of Interconnect Signal Paths Characterized from a 16nm Test Chip

An array-based test-vehicle for tracking bit-error-rate (BER) degradation of signal interconnects subject to DC electromigration (EM) stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buf...

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Bibliographic Details
Published inDigest of technical papers - Symposium on VLSI Technology pp. 1 - 2
Main Authors Pande, N., Zhou, C., Lin, MH, Fung, R., Wong, R., Wen, S., Kim, C. H.
Format Conference Proceeding
LanguageEnglish
Published Japan Society of Applied Physics (JSAP) 13.06.2021
Subjects
Bit-Error-Rate
Circuit reliability
Datapath
Degradation
Electromigration
Integrated circuit interconnections
Life estimation
Metals
Semiconductor device measurement
Signal-Interconnects
Very large scale integration
Wires
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Summary:An array-based test-vehicle for tracking bit-error-rate (BER) degradation of signal interconnects subject to DC electromigration (EM) stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. BER measurement results from four individual interconnect paths are presented and analyzed.
ISSN:2158-9682