SmartExtract: accurate capacitance extraction for SOC designs

• Published in: 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) p. 4 pp.
• Main Authors: Narasimha, U., Hill, A., Nagaraj, N.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2006
• Subjects: Capacitance; Delay; Design methodology; Dielectric constant; Dielectric materials; Digital signal processing; Etching; Instruments; Integrated circuit interconnections; Manufacturing
• ISBN: 0769525024; 9780769525020
• ISSN: 1063-9667; 2380-6923
• DOI: 10.1109/VLSID.2006.148

Most capacitance extraction tools used in SOC designs use 2.5D methods and suffer from inherent limitations in accuracy. Often accuracy is traded off in lieu of runtime. In addition, every net in a design is extracted to same level of accuracy. As interconnect RC is a significant portion of circuit performance, errors in capacitance extraction directly affects the maximum attainable chip frequency. In this paper, a new methodology for accurate capacitance extraction called SmartExtract is described. Not all nets in a design need high degree of capacitance extraction accuracy. SmartExtract exploits this scenario and enables selective accuracy of extraction based on timing criteria. Application of this methodology to 90nm and 65nm DSP designs is described.