ESD design challenges

With the scaling of CMOS technology the design of Electro-Static Discharge (ESD) protection circuits is becoming an increasingly challenging task. This challenge is mainly due to thinner gate oxide, shorter channel length, and shallower junctions. In addition, higher operational frequencies necessit...

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Bibliographic Details
Published in2009 IEEE Custom Integrated Circuits Conference pp. 1 - 2
Main Authors Sachdev, Manoj, Vuong, Hong-Ha
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2009
Subjects
CMOS technology
Design automation
Electrostatic discharge
Frequency
Integrated circuit packaging
Integrated circuit technology
Large scale integration
Paper technology
Parasitic capacitance
Protection
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Summary:With the scaling of CMOS technology the design of Electro-Static Discharge (ESD) protection circuits is becoming an increasingly challenging task. This challenge is mainly due to thinner gate oxide, shorter channel length, and shallower junctions. In addition, higher operational frequencies necessitate lower parasitic capacitance ESD protection circuits which often compromise the ESD protection level.
ISBN:1424440718
9781424440719
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2009.5280757