8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET

• Published in: Digest of technical papers - IEEE International Solid-State Circuits Conference Vol. 64; pp. 138 - 140
• Main Authors: Mishra, P., Tan, A., Helal, B., Ho, C.R., Loi, C., Riani, J., Sun, J., Mistry, K., Raviprakash, K., Tse, L., Davoodi, M., Takefman, M., Fan, N., Prabha, P., Liu, Q., Wang, Q., Nagulapalli, R., Cyrusian, S., Jantzi, S., Scouten, S., Dusatko, T., Setya, T., Giridharan, V., Gurumoorthy, V., Karam, V., Liew, W., Liao, Y., Ou, Y.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 13.02.2021
• Subjects: FinFETs; Forward error correction; Optical switches; Solid state circuits; Throughput; Transceivers
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC42613.2021.9365929

Driven by the proliferation of rich media services and a drastic increase of data availability, the demand for high-speed data transfer in the data center continues to grow at greater than 26 percent year-over-year [1]. This urges the imminent solution of top-of-rack switches in hyperscale networks with faster I/O interfaces to simultaneously support both low power and high throughput. Supporting the substantial bandwidth increase has driven the development of new electrical and optical interconnect standards which enable 100Gb/s per channel including IEEE 802.3ck and CEI-112G with PAM-4 modulation in conjunction with forward error correction (FEC) [2]. For long-reach applications, a transceiver architecture with >40dB channel equalization is critical due to the extra 8-10dB package insertion loss. To resolve those bottlenecks, this work presents an ADC-DSP based PAM-4 transceiver capable of equalizing >41.5dB lossy channels and achieving 112Gb/s per channel and 896Gb/s overall retimer throughput in 7nm FinFET.