Design of voltage scaled level converters in low power clock distribution networks

As Design Complexity is growing and Size of the individual components i.e mosfets shrinks, it led to the need for increased clock speeds, to do faster computation and propagate the clock to different subsystems of the chip. The clock to be routed must be free from clock skew and jitter. The alternat...

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Bibliographic Details
Published in2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) pp. 579 - 583
Main Authors Rajesh, A., Raju, B. L., Reddy, K. Chenna Kesava
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2016
Subjects
clock skew and Jitter
Clocks
Inverters
Level Converter (Low to high and high to Low)
Low voltage
MOS devices
multiple voltages
Power demand
Transforms
Transistors
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Summary:As Design Complexity is growing and Size of the individual components i.e mosfets shrinks, it led to the need for increased clock speeds, to do faster computation and propagate the clock to different subsystems of the chip. The clock to be routed must be free from clock skew and jitter. The alternate method for reducing power requirement is use of multi-Vdd i.e more than one supply voltage depending on the requirement, without reducing the speed in an system on chip. For this, Level Converters are required. Level converters based on Multi-Vdd are proposed in this paper. The proposed level converters are compared with the existing standard level converters. Compared to the Existing Level Converters, the proposed level converters offers significant power saving and increased speed. In this paper, 180nm MOSFETs are used. For high performance and Low power design, different types of level converters are analyzed using Cadence Tools.
DOI:10.1109/RTEICT.2016.7807888