A MP-SoC design methodology for the fast prototyping of embedded image processing system

• Published in: 2010 International SoC Design Conference pp. 384 - 387
• Main Authors: Siéler, Loïc, Dérutin, Jean Pierre, Landrault, A
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2010
• Subjects: Algorithm design and analysis; Computer architecture; Hardware; Libraries; Parallel programming; Program processors; System-on-a-chip
• ISBN: 1424486335; 9781424486335
• DOI: 10.1109/SOCDC.2010.5682889

This article proposes an original design flow for the fast prototyping of image processing on a MP-SoC (MultiProcessors System on Chip) architecture. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability of an ad hoc design methodology. This paper illustrates a new design flow that enables to instantiate a generic Homogeneous Network of Communicating Processors (called HNCP) tailored for a targeted application. The HNCP is generated with a tool that avoids fastidious manual editing operations for the designer. Specific lightweight communication functions have been developed to fasten the programming of the MP-SoC network. A case study (image texture analyzes) is presented to illustrate the proposed MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.