A method of extracting on-chip decoupling cap through board level

A method of extracting on-chip decoupling capacitance will benefit the SI/PI engineers to complete the models in PDN and this will enhance the accurate prediction of power integrity analysis. A methodology is proposed to extract and model the on-chip decoupling capacitance through the system board l...

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Bibliographic Details
Published in2008 Asia-Pacific Microwave Conference pp. 1 - 4
Main Authors Tseng, P.M., Chang, J., Tsai, F.Y., Yeh, C., Chen, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2008
Subjects
Capacitance
Capacitors
Frequency
Impedance
Power distribution
Power system modeling
Semiconductor device noise
System-on-a-chip
Testing
Voltage
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Summary:A method of extracting on-chip decoupling capacitance will benefit the SI/PI engineers to complete the models in PDN and this will enhance the accurate prediction of power integrity analysis. A methodology is proposed to extract and model the on-chip decoupling capacitance through the system board level, and good results were demonstrated.
ISBN:9781424426416
1424426413
ISSN:2165-4727
2165-4743
DOI:10.1109/APMC.2008.4958460