Modeling Data Access Contention in Multicore Architectures

Multicore processors are now part of mainstream computing. However, data access contention among multiple cores is a significant performance bottleneck in utilizing these processors. Typically, memory hierarchies in multicore architectures use shared last level cache or shared memory. As multiple co...

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Bibliographic Details
Published in2009 15th International Conference on Parallel and Distributed Systems pp. 213 - 219
Main Authors Xian-He Sun, Byna, S., Holmgren, D.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2009
Subjects
Analytical models
Bandwidth
Computer architecture
Concurrent computing
data access contention
Delay
Modeling
Multicore processing
multicore processors
Parallel processing
performance prediction
Predictive models
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Summary:Multicore processors are now part of mainstream computing. However, data access contention among multiple cores is a significant performance bottleneck in utilizing these processors. Typically, memory hierarchies in multicore architectures use shared last level cache or shared memory. As multiple cores concurrently send requests to access data from these shared memory hierarchy levels, their capacity to serve all the requests is overwhelming and causes performance bottlenecks. In this paper, we introduce simple analytical models for predicting the occurrence of data access contention and provide a guideline for choosing optimal number of cores in running an application without causing data access contention. We verify our models by comparing the predicted optimal number of cores without causing data contention with the measured value in running MIMD Lattice Computation (MILC) application. The proposed analytical models are accurate and promising in guiding data access optimizations to improve multicore utilization.
ISBN:9781424457885
1424457882
ISSN:1521-9097
2690-5965
DOI:10.1109/ICPADS.2009.121