Network processing performability evaluation on heterogeneous reliability multicore processors using SRN model

• Published in: 2009 IEEE International Symposium on Parallel & Distributed Processing pp. 1 - 6
• Main Authors: Ungsunan, P.D., Chuang Lin, Yang Wang, Yi Gai
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: Environmental factors; heterogeneous multicore; Low voltage; Multicore processing; multiprocessing systems; network processing; Noise reduction; Performance evaluation; Power system modeling; Power system reliability; reliability; Semiconductor device reliability; Telecommunication traffic; Traffic control
• ISBN: 9781424437511; 1424437512
• ISSN: 1530-2075
• DOI: 10.1109/IPDPS.2009.5161188

Future network systems and embedded infrastructure devices in ubiquitous environments will need to consume low power and process large amounts of network packet traffic. In order to meet necessary high processing efficiency requirements, future processors will have many heterogeneous cores with reduced reliability due to low voltage, small transistor sizes, semiconductor wearout, and environmental factors such as noise and interference. It will be necessary for multi-core network infrastructure software to mitigate transient hardware faults to maintain acceptable system reliability. Applications such as packet processing can benefit from the reliability versus performance tradeoff. We propose a model based on stochastic reward nets to evaluate the performance vs. reliability tradeoff of unreliable embedded multi-core network processors, and apply this model to a multi-core packet processing application.