Cost and power/performance optimized 20nm SoC technology for advanced mobile devices

• Published in: 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers pp. 1 - 2
• Main Authors: Nallapati, G., Zhu, J., Wang, J., Sheu, J. Y., Cheng, K. L., Gan, C., Yang, D., Cai, M., Cheng, J., Ge, L., Chen, Y., Bucki, R., Bowers, B., Vang, F., Chen, X., Kwon, O., Yoon, S., Wu, C. C., Chidambaram, Pr, Cao, M., Fischer, J., Terzioglu, E., Mii, Y. J., Yeap, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2014
• Subjects: Computer architecture; Layout; Logic gates; Metals; Mobile communication; Optimization; Performance evaluation
• ISBN: 9781479933310; 1479933317
• ISSN: 0743-1562
• DOI: 10.1109/VLSIT.2014.6894414

A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving ~2× gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.