Layered T comparator design using quantum-dot cellular automata

Comparator is crucial block in Central Processing Unit especially in the process of "Data Searching-Sorting" where huge amount of data needs to be searched during the Database Management operations. In this work, the logic design of 1-bit Quantum Cellular Automata (QCA) comparator has been...

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Bibliographic Details
Published in2017 Devices for Integrated Circuit (DevIC) pp. 90 - 94
Main Authors Roy, Soudip Sinha, Mukherjee, Chiradeep, Panda, Saradindu, Mukhopadhyay, Asish Kumar, Maji, Bansibadan
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2017
Subjects
1-bit Comparator
Automata
Fault tolerance
Fault tolerant systems
Integrated circuits
Layered T Gate
Layout
Logic gates
Quantum dots
Quantum-dot Cellular Automata
universal gates
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Summary:Comparator is crucial block in Central Processing Unit especially in the process of "Data Searching-Sorting" where huge amount of data needs to be searched during the Database Management operations. In this work, the logic design of 1-bit Quantum Cellular Automata (QCA) comparator has been proposed using the Layered-T AND and OR Gates. The proposed comparator layout needs 9.02% less effective area compared to the best reported design so far. The effect of cell misplacements on the proposed layout is thoroughly investigated. Moreover, the other QCA design metrics such as O-Cost, CostI are calculated for the proposed 1-bit Layered T Comparator circuit. The functionality of the proposed circuit is verified by computer aided design tool QCADesigner 2.0.3.
DOI:10.1109/DEVIC.2017.8073913