A 2.5-Gb/s clock and data recovery circuit with ΔΣ-modulated fractional frequency compensation

• Published in: TENCON 2010 - 2010 IEEE Region 10 Conference pp. 2460 - 2463
• Main Authors: Ching-Yuan Yang, Wei-Shuo Lin, Jung-Mao Lin, Hsin-Ming Wu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2010
• Subjects: Clocks; Frequency modulation; Jitter; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators
• ISBN: 9781424468898; 1424468892
• ISSN: 2159-3442; 2159-3450
• DOI: 10.1109/TENCON.2010.5685929

A 2.5-Gb/s clock and data recovery (CDR) circuit is presented, which employs an oversampling technique to recovery the data and an offset-frequency calibrated technique to compensate the frequency error between input rate and output clock. The offset-frequency calibrated technique is based on the ΔΣ modulated phase-lock-loop topology that can calibration frequency offset ±200 MHz. Simulated by 0.18-μm CMOS technology, the retimed clock and the recovery data have the jitter of 10.1 ps and 11.7 ps, respectively (peak-to-peak). It consumes power dissipation of 152 mW under a 1.8-V supply.