Efficient Forced Convergence algorithm for low power LDPC decoders

This paper proposes an efficient Forced Convergence (FC) algorithm to reduce the computational complexity of LDPC decoders. To reduce the computational complexity, the proposed algorithm uses only one threshold value and two conditions of variable nodes (VNs) while the existing FC algorithm uses two...

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Bibliographic Details
Published in2013 International SoC Design Conference (ISOCC) pp. 372 - 373
Main Authors Byung Jun Choi, Myung Hoon Sunwoo
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2013
Subjects
Algorithm design and analysis
Bit error rate
Computational complexity
Convergence
Decoding
error correction codes
forced convergence
low density parity check (LDPC)
low power decoder
Parity check codes
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Summary:This paper proposes an efficient Forced Convergence (FC) algorithm to reduce the computational complexity of LDPC decoders. To reduce the computational complexity, the proposed algorithm uses only one threshold value and two conditions of variable nodes (VNs) while the existing FC algorithm uses two threshold values and two conditions. The simulation results show that the proposed algorithm achieves the bit error rate (BER) performance close to the typical Min-Sum algorithm. however, it can significantly reduce the computational complexity compared to the existing FC algorithm.
DOI:10.1109/ISOCC.2013.6864054