5G NR LDPC Decoding Performance Comparison between GPU & FPGA Platforms

• Published in: 2019 IEEE Long Island Systems, Applications and Technology Conference (LISAT) pp. 1 - 6
• Main Authors: Aronov, Alex, Kazakevich, Leonid, Mack, Jane, Schreider, Fred, Newton, Scott
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2019
• Subjects: 3GPP; 5G NR; component; FPGA; GPU; LDPC
• ISSN: 2642-8873
• DOI: 10.1109/LISAT.2019.8816821

Fifth Generation NR is the global standard for the wireless air interface that promises to deliver high reliability and low end-to-end latency while delivering ultra-high-speed data. The 3 rd Generation Partnership Project (3GPP) has standardized Low Density Parity Check (LDPC) coding as the solution to satisfy the channel coding demands of 5G NR. The trend towards virtualization of traditionally hardware functions to reduce development and equipment costs motivates a GPU based SDR platform for 5G NR. To that end, we developed an optimized 3GPP compliant LDPC decoder [1]. Performance data was collected on this enhanced decoder algorithm hosted on both a field programmable gate array (FPGA) and a graphic processing unit (GPU) platform. The advantages and disadvantages of FPGA and GPU technology for LDPC decoding are discussed. Both implementations align with Standards, but we show that the GPU solution exhibits larger latency primarily due to memory accesses. Future work for improving the LDPC decoder latency on the GPU is described.