A 24GS/s 6b ADC in 90nm CMOS

This paper presents a 24 GS/s 6 b ADC in 90 nm CMOS with the highest ENOB up to 12 GHz input frequency and lowest power consumption of 1.2 W compared to ADCs with similar performance. It uses an interleaved architecture of SAR type self-calibrating converters operating from 1 V supply combined with...

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Bibliographic Details
Published in2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers pp. 544 - 634
Main Authors Schvan, Peter, Bach, Jerome, Falt, Chris, Flemke, Philip, Gibbins, Robert, Greshishchev, Yuriy, Ben-Hamida, Naim, Pollex, Daniel, Sitch, John, Wang, Shing-Chi, Wolczanski, John
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2008
Subjects
Calibration
Circuits
Clocks
Field programmable gate arrays
Frequency estimation
Jitter
Packaging
Sampling methods
Signal sampling
Yield estimation
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Summary:This paper presents a 24 GS/s 6 b ADC in 90 nm CMOS with the highest ENOB up to 12 GHz input frequency and lowest power consumption of 1.2 W compared to ADCs with similar performance. It uses an interleaved architecture of SAR type self-calibrating converters operating from 1 V supply combined with an array of 2.5 V T/Hs with delay, gain and offset-calibration capability.
ISBN:1424420105
9781424420100
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2008.4523298