Implementation of Split-Radix Fast Fourier Transform on FPGA

Nowadays, portable systems are developed especially for signal processing, where the principal challenge is to find circuits with less area and power consumption. One of the most powerful tools in the area of Signal Processing is the Fast Fourier Transform (FFT). Many algorithms have been developed...

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Bibliographic Details
Published in2010 VI Southern Programmable Logic Conference (SPL) pp. 167 - 170
Main Authors Watanabe, Cynthia, Silva, Carlos, Muñoz, Joel
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2010
Subjects
Circuits
Computer architecture
Energy consumption
Fast Fourier transforms
Field programmable gate arrays
Frequency
Laboratories
Microelectronics
Runtime
Signal processing algorithms
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Summary:Nowadays, portable systems are developed especially for signal processing, where the principal challenge is to find circuits with less area and power consumption. One of the most powerful tools in the area of Signal Processing is the Fast Fourier Transform (FFT). Many algorithms have been developed to improve its computation time; one of them is the Split Radix Fast Fourier Transform (SRFFT) which reduces the number of complex computation. Therefore, a new architecture is proposed to compute the SRFFT. Although the runtime of this design is high, it has some important profits like a flexible number of inputs N=2 P ; few resources required such as combinational functions, logic registers and memory.
ISBN:9781424463091
1424463092
DOI:10.1109/SPL.2010.5483018