A hybrid built-in self-test scheme for DRAMs

This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algori...

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Bibliographic Details
Published inVLSI Design, Automation and Test(VLSI-DAT) pp. 1 - 4
Main Authors Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2015
Subjects
Algorithm design and analysis
Built-in self-test
Generators
Radiation detectors
Random access memory
Read only memory
Registers
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Summary:This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.
DOI:10.1109/VLSI-DAT.2015.7114502