Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication

• Published in: 2012 12th International Conference on Application of Concurrency to System Design pp. 62 - 71
• Main Authors: Mundy, A., Mak, T., Yakovlev, A., Davidson, S., Furber, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2012
• Subjects: Algorithm design and analysis; Approximation algorithms; Bellman Equation; Complexity theory; Computational efficiency; Concurrent computation; Convergence; Dynamic programming; Dynamic Programming network; Educational institutions; Graph analysis
• ISBN: 9781467316873; 1467316873
• ISSN: 1550-4808; 2374-8567
• DOI: 10.1109/ACSD.2012.12

The analysis of large scale, complex networks using dynamic programming is of great use in many scientific and engineering disciplines. Current applications often require the analysis of scale-free networks with many millions of nodes and edges, presenting a huge computational challenge. Employing a distributed networks-on-chip infrastructure presents a unique opportunity of delivering power efficient and massive parallel accelerations. However, bursting and asymmetric communications across cores could create instant network saturation and lead to packet loss and performance degradation. In this paper, we present a moderated communication methodology that enables a balanced channel usage and network topological adaptation for improved performance. A novel analytical communication model for NoC is developed and leads to a theoretical bound of the on-chip communication cost estimate. Performances of the many-core computation and the proposed methods are rigorously evaluated using the real 18-core Spinnaker chip. We demonstrate a 10x speed-up in analysis convergence and a 42% reduction in instantaneous Packet Injection Rate based on benchmark networks.