Analysis of the FinFET parasitics for improved RF performances

FinFET architecture results in high level of parasitics that offset the performance gain that can be achieved through gate length scaling. In this work, we investigate technological solutions both at the process integration and layout levels to alleviate these limitations. Layout guidelines are deri...

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Bibliographic Details
Published in2007 IEEE International SOI Conference pp. 37 - 38
Main Authors Parvais, B., Dehan, M., Subramanian, V., Mercha, A., San, K.T., Jurczak, M., Groeseneken, G., Sansen, W., Decoutere, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2007
Subjects
FinFETs
Guidelines
Instruments
Integrated circuit interconnections
MOSFETs
Parasitic capacitance
Performance analysis
Radio frequency
Roentgenium
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Summary:FinFET architecture results in high level of parasitics that offset the performance gain that can be achieved through gate length scaling. In this work, we investigate technological solutions both at the process integration and layout levels to alleviate these limitations. Layout guidelines are derived to improve the RF performance. For an optimized layout folding, experiments indicate 15% gain in f T .
ISBN:9781424408795
1424408792
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.2007.4357841