Model-based Design Space Exploration for RTES with SysML and MARTE

The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including real time embedded systems (RTES). An important goal to achieve is the implementation and use of these models in all the steps of...

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Bibliographic Details
Published in2008 Forum on Specification, Verification and Design Languages pp. 203 - 208
Main Authors Mura, M., Murillo, L.G., Prevostini, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2008
Subjects
Analytical models
Hardware
Mathematical model
Real time systems
Resource management
Time factors
Unified modeling language
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Summary:The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including real time embedded systems (RTES). An important goal to achieve is the implementation and use of these models in all the steps of a common design flow. One of these steps is the design space exploration (DSE), which helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications; for RTES this step is particularly hard as it should include scheduling analysis in order to proof the time validity after the mapping. This paper presents some guidelines on how to use SysML and MARTE profiles to identify design points fulfilling the timing constraints of an RTES, and thus allowing to automate DSE analysis within the system design phase.
ISBN:9781424422647
1424422647
DOI:10.1109/FDL.2008.4641446