A 90nm 1-4.25-Gb/s Multi Data Rate Receiver for High Speed Serial Links

This paper describes the design of a receiver that supports the operation from 1 to 4.25-Gb/s, enabling a single macro to satisfy different protocols. The receiver performs equalization to compensate for interconnect ISI, achieves 10 mV sensitivity at 4.25-Gb/s by using offset corrected amplificatio...

Full description

Saved in:
Bibliographic Details
Published in2006 IEEE Asian Solid-State Circuits Conference pp. 391 - 394
Main Authors Lidong Chen, Spagna, F., Marzolf, P., Wu, J.K.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2006
Subjects
Band pass filters
Bandwidth
Clocks
Digital control
Equalizers
Intersymbol interference
Phase control
Power system interconnection
Protocols
Signal generators
Online AccessGet full text

Cover

More Information
Summary:This paper describes the design of a receiver that supports the operation from 1 to 4.25-Gb/s, enabling a single macro to satisfy different protocols. The receiver performs equalization to compensate for interconnect ISI, achieves 10 mV sensitivity at 4.25-Gb/s by using offset corrected amplification, and performs clock-data-recovery with a digital algorithm that controls a recovered clock out of a phase interpolator. The receiver has been validated in 90 nm CMOS with 45 mW at 1.1 V supply voltage and demonstrated to achieve link over 30-meter AGW24 cable at 3.125 Gb/s with BER<10 -5 .
ISBN:9780780397347
0780397347
DOI:10.1109/ASSCC.2006.357933