32 Bit re-configurable RISC processor design and implementation for BETA ISA with inbuilt matrix multiplier

• Published in: 2016 Sixth International Symposium on Embedded Computing and System Design (ISED) pp. 112 - 116
• Main Authors: Singh, Raj Prakash, Vashishtha, Ankit K., Krishna, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2016
• Subjects: BETA ISA; Computer architecture; Field programmable gate arrays; FPGA design; Hardware; Hardware design languages; HDL implementation; matrix multiplication; Radiation detectors; re-configurable hardware; Reduced instruction set computing; Registers; RISC processor
• ISSN: 2473-9413
• DOI: 10.1109/ISED.2016.7977065

A 32 bit re-configurable RISC processor design has been proposed in this paper. The design is based on BETA Instruction Set Architecture, introduced by MIT, USA with precise no. of instructions for high speed computing using general purpose RISC processors. In our proposed design, a new non-pipelined and re-configurable data path has been introduced to provide inbuilt matrix multiplication functionality additional to BETA ISA. The incorporated matrix multiplier enables this processor to be a great option for DSP applications with signal and image processing requirements. Von-Neumann architecture has been followed for memory implementation with two separate 32-bits address and data lines. Hence, this processor design can support up to 4 GB of external memory. The design has thirty 32bit sized internal general purpose registers for direct instruction fetch. The design is implemented using Verilog HDL. Further, synthesis and function verification has been done on Xilinx Virtex 6 using Xilinx Tool suit.