Gate-overlapped-source heterojunction tunnel tri-gate FinFET

We present a simulation study of gate-overlapped-source heterojunction tunnel Tri-gate FinFET (GoS-HTTFinFET). The small bandgap material (Ge) in the source results in an improved tunneling rate, while the wide bandgap material (Si) in the channel/drain reduces ambipolar leakage. Here lateral (so ca...

Full description

Saved in:
Bibliographic Details
Published in2017 Devices for Integrated Circuit (DevIC) pp. 561 - 564
Main Authors Kumar, Pankaj, Roy, Saurav, Baishya, Srimanta
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2017
Subjects
Doping
FinFETs
gate-overlapped-source (GoS)
Heterojunction tunnel Tri-gate FinFET (HTTFinFET)
Heterojunctions
Integrated circuit modeling
line tunneling
Logic gates
point tunneling
Semiconductor process modeling
subthreshold slope (SS)
Tunneling
Online AccessGet full text

Cover

More Information
Summary:We present a simulation study of gate-overlapped-source heterojunction tunnel Tri-gate FinFET (GoS-HTTFinFET). The small bandgap material (Ge) in the source results in an improved tunneling rate, while the wide bandgap material (Si) in the channel/drain reduces ambipolar leakage. Here lateral (so called point tunneling) tunneling relative to vertical (so called line tunneling) tunneling and the channel gradual doping improves the subthreshold slope (SS) upto ~39 mV/decade. Stack of two different oxide materials (low-k and high-k) are used to reducde surface roughness scattering due to high-k dielectric. A very steep subthreshold slope (SS) and very low off-currents (few fA/μm) is observed for the proposed device. Improvement in the SS has been realized by gradual channel doping. Due to this steep SS, an I on /I off ratio of the order of ~2×10 10 , and drive current (Ion ~120 μA/μm) have been observed.
DOI:10.1109/DEVIC.2017.8074013