Advances on III-V on Silicon DBR and DFB Lasers for WDM Optical Interconnects and Associated Heterogeneous Integration 200mm-Wafer-Scale Technology

• Published in: 2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) pp. 1 - 6
• Main Authors: Menezo, S., Duprez, H., Descos, A., Bordel, D., Sanchez, L., Brianceau, P., Fulbert, L., Carron, V., Ben Bakir, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2014
• Subjects: Distributed Bragg reflectors; Fiber lasers; Optical waveguides; Silicon; Surface emitting lasers; Waveguide lasers
• ISSN: 1550-8781; 2374-8443
• DOI: 10.1109/CSICS.2014.6978538

In the absence of practically efficient lasers achievable directly in Silicon or other group IV materials, Si-photonic transmitter sources must be made by "Hybrid integration" of III-V chips or "Heterogeneous integration" with III-V gain materials. "Hybrid integration" technologies consist in integrating processed (and finished) chips in a photonic microsystem. One commercial solution (from LUXTERA) makes use of a InP-bulk- processed laser-chip [3]. The laser chip is attached to the PIC, and its light is coupled into the PIC- waveguide by means of a lens, followed by an optical isolator, and a mirror for directing the light to a surface grating coupler in the Si-PIC. Other approaches (from KOTURA/ORACLE) consist in but-coupling a III-V- semiconductor reflective-SOA to the PIC-3μm- thick-Si-waveguide that comprises a Bragg-mirror for defining the laser cavity [4]. This forms an external-cavity DBR laser, with reported Waveguide-Coupled Wall-Plug-Efficiencies (WC-WPE) for the uncooled lasers of up to 9.5% at powers of 6 mW. In spite of the good demonstrated performances, this solution requires an accurate alignment between the R-SOA and the Si-PIC, limiting the capability for a low cost fabrication. As a more economical route that we opted for, "Heterogeneous integration" technologies were proposed [5], [6] together with new laser architectures. An InP-wafer having the III-V-gain- layers grown on top is bonded with loose alignment requirements (~50μm), the III-V gain-layers facing down to the bottom Silicon-On- Insulator (SOI) wafer on which silicon waveguides are pre- processed. In a more economical route, the InP-substrate having the laser III-V-gain- layers on top is first diced, and the dies are bonded where needed. Then the InP-substrate is removed, and the laser process is continued on the remaining III-V gain epi-layers, in a regular wafer level process flow. Putting the expensive III-V-gain material only where needed saves on cost. In addition to lower cost, photonic integration promises improved reliability and performances and reduced footprints over discrete components systems. This paper will report on our recent advances on both, 1) the developed III-V on Silicon lasers (DBR and DFB types) built up from heterogeneous integration, and, 2) the development of the integration technology for processing the lasers on 200mm-wafers, with industrial CMOS tools at very low cost.