Design of 1-bit full adder using NMOS based negative differential resistance

In this paper a new implementation technique of 1-bit full adder using Negative Differential Resistance (NDR) circuit composed of N-MOSFETs is presented. The design is based on Monostable to Bistable transition logic element (MOBILE) theory. In this circuit peak current level of the load and driver...

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Bibliographic Details
Published in2017 Devices for Integrated Circuit (DevIC) pp. 630 - 636
Main Authors Chowdhury, Subhajit Dutta, Chaudhuri, Rajarshi Roy, Sarkar, Mili
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2017
Subjects
Adders
Full Adder
Integrated circuits
Logic gates
MOSFET
N-channel Metal Oxide Semiconductor Field effect transistor (NMOS)
Negative differential resistance (NDR)
Power demand
Resistance
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Summary:In this paper a new implementation technique of 1-bit full adder using Negative Differential Resistance (NDR) circuit composed of N-MOSFETs is presented. The design is based on Monostable to Bistable transition logic element (MOBILE) theory. In this circuit peak current level of the load and driver NDR is modulated by controlling the gate voltage of n-MOS device connected in parallel to the NDR element according to the logic input thus producing different output for different input. The major advantage of this NDR based full adder circuit is its power efficiency and simplicity. High speed of operation can also be obtained using NDR element. In the circuit, the current magnitudes are in the order of a few microamperes leading to lower power consumption which in turn ensures lower heat dissipation, which facilitates higher stability and reliability. The circuit is designed based on the standard 0.18μm technology. The circuit simulation is done using software, CADENCE and MATLAB.
DOI:10.1109/DEVIC.2017.8074027